Information transfer in digital logic may happen either between logic located in the same clock domain, or between different clock domain regions. Whenever a transfer happens within the same clock domain, the correctness of the information transfer can be guaranteed by specific digital design tools (synthesis, static timing analysis, etc.). However, for an information transfer between different clock domains, the data correctness can typically not be guaranteed by the tools due to physical phenomenon of metastability which cannot be avoided because the data created in source clock domain can change at any moment relative to destination clock domain. In those cases the data correctness has to be guaranteed by digital design methods. Thus, efficient approaches that allow guaranteeing data correctness for data transfers over clock domain boundaries are desirable.